My final post here about exxos

Started by Petari, 18-01-2019, 10:28:48

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I really don't want to talk for longer about exxos, his forum, what happened there. Here are some threads (rather my blogs) about it.
So, I think that this will be good as my final post about exxos. His posts just talk for self. I don't think that there is need for any comment about his knowledge level.
Quoting most interesting part from it: "I am slightly confused over the CS0 and CS1 signals which are linked to A5.
According to the ATA spec, they are used to select upper or lower 8bit bank select in the drive. Fair enough.. but the CPU has a 16bit bus, so why doesn't the data transfer as a 16bit block ?!
The CPU would actually have to do 2 bus cycles I assume to change the A5 for upper and lower 8bits ? Would seem a bit pointless having a 16bit drive and interface, and yet its looking like its driven as a 8bit device "
Interesting - and all it is written after he 'designed' IDE adapter for ST. Which he did not take effort to test himself. Anyone thinking that what and how he does is totally insane ?