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TOS 2.x address decoder in STM


I have installed two 512Kb flash-ROMs (29c040) in my 520STM. By switching the two upper address lines this gives me four "banks" and four different TOS-versions to play with. TOS 1.x works fine, but I can't get 2.06 to work.

My STM differs a little bit from the schematics I found (, it has two ROMs and not six. ROM0, ROM1 and ROM2 is ORed in a 7411, and the ORed ROM-signal is routed too the two ROMs through a jumper. ROM0 and ROM1 is routed directly to the four vacant ROM-slots without jumpers. Looks very similar to how it's done my Mega 2. I can switch to six ROMs mode by flipping the jumper, thus routing ROM2 alone to the two ROMs.

Now, I programmed a GAL16V8D with the Jedec-file from your Mega ST IDE interface ( and set it up on a breadboard. I only connected the signals that's used in the CER equation - AS, A18, A19, A20, A21, A22, A23, RW and ROM2. AS, RW and the address lines were connected directly to the CPU. The ORed ROM-signal was separated from the ROMs by removing the jumper, and the ORed signal was fed to the GAL's ROM2-pin. The CER signal from the GAL was then connected to the ROMs via the other end of the jumper.

This works fine with TOS 1.x, but not at all with TOS 2. Since it works with TOS 1 the ROMs must be getting the ORed ROM-signal via the GAL. Any idea on what I'm doing wrong?

Edit: Never mind! Just as I submitted this I realized that I had forgotten to connect DTACK :)

DTACK did the trick... IDE next.


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